Devices and methods for effecting electrical interconnection between two conductors are generally known. A specialized area of such interconnection has been recently expanding with the advent of integrated circuit technology. The chip of the integrated circuit must be electrically interconnected with the overall device by some means in order to effect interfacing between the integrated circuit and the overall device.
In the manufacturing process for making integrated circuit devices, each integrated circuit must be tested for operativeness. Thus, another application for electrical interconnection of an integrated circuit device is with a tester apparatus. To assure proper testing, the electrical interface must be of high reliability so that tested integrated circuits are not falsely found defective due to a poor electrical interconnection rather than to actual defectiveness in the integrated circuit. Testing apparatus which connect an integrated circuit device with a printed circuit board are generally referred to as a device under test (DUT) boards.
Several technologies for packaging a semi-conductor chip into an integrated circuit device have developed. These may be generally categorized as pin grid array (PGA) systems and leaded semi-conductor devices. The leaded semi-conductor devices include plastic leaded chip carriers (PLCC), dual in-line packages (DIP) and Quad Flat Pack (QFP). Each packaging type requires a particular array of contacts to be interconnected with a printed circuit board.
A further specialized area of interconnecting electrical contacts focuses on the interconnection of two printed circuit boards. These interconnections have applications utilizing insertable boards, such as memory cards, or multi-chip boards which are highly miniaturized and integrated.
All of the electrical interconnect applications described above have mechanical and electrical requirements and problems associated therewith. Each of these requirements and problems bear upon the structure which should be employed to connect the integrated circuit and the printed circuit board or two printed circuit boards.
A first mechanical consideration to be taken into account in designing an interconnect system is that a wiping action should be accomplished between the contact itself and a lead of the integrated circuit by which the contact is engaged. The wiping action functions to effect maximization of the interconnect in view of oxide build-up which can occur. In effect, the wiping action enables a good interface to be accomplished between the contact and a lead of the integrated circuit. This wiping action should be effected both on the integrated circuit contact and the printed circuit board contact. Likewise, it should be effected on both printed circuit board terminals if such apparatus is utilized for interconnecting more than one printed circuit board.
A preferred contact for the electrical interconnection of the above devices should be high speed and provide a very short path of connection. Derivatively, such a contact should have a low inductance without having a controlled impedance requirement. Further, methods of interconnection require a device that allows a mechanical compliant connection that can compensate for variations in flatness, while allowing the above-described wiping action. The objective is to develop a good low resistance electrical interconnection that is stable for a period of time. The ideal stable connection is termed a "gas-tight connection". This term refers to a connection where sufficient force and wipe action is applied between surfaces to provide a self-cleaning action to prevent air from penetrating. It is recognized that air is the prime source of non-electrical conductive oxides that form on surfaces and that air can carry and deposit forms of contaminations such as dirt, grease, oil and others.
Johnson recently disclosed in U.S. Pat. Nos. 5,069,629 (issued Dec. 3, 1991) and 5,207,584 (issued May 4, 1993) electrical interconnect contact systems which are directed to addressing both mechanical and electrical dictates outlined above. The disclosure of these references is incorporated herein by reference.
The disclosures of Johnson are directed to a generally planar contact which is received within one or more slots of a housing. Each contact is of a generally S-shaped design and supported at two locations (the hook portions of the S) by either a rigid first element or an elastomeric second element. As disclosed, the Johnson electrical interconnect provides a wiping action which enables a good interface to be accomplished between the contact and the lead of the integrated circuit. However, the degree of movement to effect the wiping action is somewhat limited by mounting the contact from two elements. Movement is further limited by the structural shape of the contact in relation to its two supports. The physical arrangement between the integrated circuit and printed circuit board is limited to applications wherein the integrated circuit device is disposed between the contacts of the device as spaced by the distance from one surface of the housing to an opposing parallel surface.
A number of other methods for connecting integrated circuits, such as PGA devices, with a printed circuit board are known. It is believed that limitations to these systems are the contact length and the usual requirement of mounting the contacts in through-holes located in a printed circuit board. The contact and through-hole mounting limits the mounting speed of the semi-conductor device while inducing discontinuities and impedance which cause signal reflections back to the source. Further, the design causes high lead inductance and thus problems with power decoupling and result in cross-talk with closely adjacent signal lines.
U.S. Pat. No. 4,894,022 discloses a solderless surface mount card edge connector. This device combines the use of a compliant contact with a mechanical clamping system that can interconnect two printed circuit boards or interconnect an integrated circuit to a printed circuit board. The limitation with this system is the complexity of the mechanical clamping system that limits the ability to simply connect and disconnect the mated terminals.
Another known method that has been used to interconnect terminals is an elastomeric sheet material that has either conductor strips or columns embedded therein. The elastomeric sheet material allows a compliant interconnection between the ends of the semi-conductor device, such as PGA device, and corresponding terminals on a printed circuit board.
Another prior art structure which seeks to accomplish the present invention is known as the Yamaichi contact. This type of contact includes an L-shaped support having a cantilevered contacting portion mounted at the distal end of the generally horizontal leg of the inverted, L-shaped support and extending generally parallel to that leg. The distal end of the contacting portion is upwardly turned so that a point thereof is engageable by a lead on an integrated circuit device to be contacted. The support, in turn, is engaged with or through a pad or terminal portion of a printed circuit board. The cantilevered portion of the Yamaichi contact is somewhat flexible to facilitate a wiping action. However, as designed, the Yamaichi contact as susceptible to bending of the lead on the integrated circuit. Further, the Yamaichi device does not sufficiently consider electrical considerations.
U.S. Pat. No. 4,445,735 which issued on May 1, 1984 illustrates another type of electrical connection device. The device of that patent serves to establish an electrical connection between contacts of a circuit network on a substrate and contact pads of a conductor network on a printed circuit board. This device is an improvement over the Yamaichi contact by operating at a higher speed and lower inductance. The device has elastomeric means for mounting one or more contacts in the housing. The elastomeric biasing and mounting enables a wiping action to be effected at both upper and lower ends of the contact. That is, both the end which engages an integrated circuit lead and the end which engages a printed circuit board contact pad can be wiped across the surfaces intended to be contacted.
The device of the '735 patent, however, retains some limitations. While some wiping action is afforded at both upper and lower ends of the contact, the amount of such wiping action is relatively limited because of the elastomeric elements being used generally for effecting biasing rather than free-floating suspension of the contact. As a result of the mounting means incorporated in the '735 patent, there will be a primary tendency for traction of the contact point in a generally vertical direction, but there will be only a small component of lateral movement to effect wiping. Additionally, because of the lack of any sufficient free-floating effect, lead bending on an integrated circuit tester can occur.
Accordingly, a need exists for an improved electrical interconnect system to be utilized for interconnecting integrated circuit devices with printed circuit boards or for interconnecting multiple printed circuit boards. The interconnecting device should be of relatively inexpensive design yet provide high speed, low inductance, solderless electrical interconnection. Further, the design should include compliant contacts which compensate for irregularities on the surface and other phenomena between the devices by incorporating free-floating of the contacts. Finally, the contacts should provide controlled wiping action to assure stable interconnection.
The present invention addresses these needs as well as other problems associated with electrical interconnect systems. The present invention also offers further advantages over the prior art and solves problems associated therewith.